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Freescale Semiconductor /MKV10Z7 /SIM /SOPT7

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Interpret as SOPT7

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0000)ADC0TRGSEL 0 (0)ADC0PRETRGSEL 0 (0)ADC0ALTTRGEN 0 (0000)ADC1TRGSEL 0 (0)ADC1PRETRGSEL 0 (0)ADC1ALTTRGEN 0 (00)ADC0ALTCLKSRC 0 (00)ADC1ALTCLKSRC

ADC0PRETRGSEL=0, ADC0TRGSEL=0000, ADC0ALTCLKSRC=00, ADC1ALTTRGEN=0, ADC0ALTTRGEN=0, ADC1ALTCLKSRC=00, ADC1TRGSEL=0000, ADC1PRETRGSEL=0

Description

System Options Register 7

Fields

ADC0TRGSEL

ADC0 Trigger Select

0 (0000): External trigger pin input (PDB0_EXTRG)

1 (0001): HSCMP0 output

2 (0010): HSCMP1 output

4 (0100): DMA channel 0 transfer last write complete

5 (0101): DMA channel 1 transfer last write complete

6 (0110): DMA channel 2 transfer last write complete

7 (0111): DMA channel 3 transfer last write complete

8 (1000): FTM0 trigger

9 (1001): FTM1 trigger

10 (1010): FTM2 trigger

14 (1110): LPTMR0 trigger
ADC0PRETRGSEL

ADC0 Pre-trigger Select

0 (0): Pre-trigger A for ADC0. Clearing this field will result in ADHWTSA=1 and ADHWTSB=0.

1 (1): Pre-trigger B for ADC0. Setting this bit will result in ADHWTSA=0 and ADHWTSB=1.
ADC0ALTTRGEN

ADC0 Alternate Trigger Enable

0 (0): PDB trigger selected for ADC0

1 (1): Alternate trigger selected for ADC0 as defined by ADC0TRGSEL
ADC1TRGSEL

ADC1 Trigger Select

0 (0000): External trigger pin input (PDB0_EXTRG)

1 (0001): HSCMP0 output

2 (0010): HSCMP1 output

4 (0100): DMA channel 0 transfer last write complete

5 (0101): DMA channel 1 transfer last write complete

6 (0110): DMA channel 2 transfer last write complete

7 (0111): DMA channel 3 transfer last write complete

8 (1000): FTM0 trigger

9 (1001): FTM1 trigger

10 (1010): FTM2 trigger

14 (1110): LPTMR0 trigger
ADC1PRETRGSEL

ADC1 Pre-trigger Select

0 (0): Pre-trigger A for ADC1. Clearing this field will result in ADHWTSA=1 and ADHWTSB=0.

1 (1): Pre-trigger B for ADC1. Setting this bit will result in ADHWTSA=0 and ADHWTSB=1.
ADC1ALTTRGEN

ADC1 Alternate Trigger Enable

0 (0): PDB trigger selected for ADC1

1 (1): Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
ADC0ALTCLKSRC

ADC0 ALT Clock Source Select

0 (00): OUTDIV5 output

1 (01): MCGIRCLK

2 (10): OSCERCLK
ADC1ALTCLKSRC

ADC1 ALT Clock Source Select

0 (00): OUTDIV5 output

1 (01): MCGIRCLK

2 (10): OSCERCLK

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data